Design Consideration of Dual Threshold Logic for High Performance and Ultralow Power Carry Look-Ahead Adder

This paper presents the design of high performance and ultralow power 8-bit carry-look-ahead adder circuits using two-phase modified dual-threshold voltage (dual-VT) domino logic method with the feed through logic concept. The proposed concepts are provides lower delay and dynamic power consumption; due to these two advantages it perform better in high fan-out and high switching frequencies. The FTL logic functions can be cascaded in a domino-logic without a need for the intervening inverters. The PMOS high threshold VT keeper increases the circuit speed and reduces the average power consumption. In addition NMOS switch added for avoiding charge sharing problem in pre-charging mode. The additions of two 8-bit binary operands are executed in two cycles. It found that, the circuit is suitable for long adders; the dynamic power consumption is also drastically reduced by more than 50% by the measurement results. This proposed CLA method reducing power (50%) and propagation time delay (around 20%).